Utilizing block size variability to enhance instruction fetch rate

In the past, instruction fetch speeds have been improved by using cache schemes that capture the actual program flow. In this paper, we elaborate on the architecture and operation of an instruction cache named Variable-Sized Block Cache (VSBC) that also makes use of the dynamic behavior of a program...

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Detalles Bibliográficos
Autores principales: Beg, Azam, Chu, Yul
Formato: Articulo
Lenguaje:Inglés
Publicado: 2007
Materias:
Ciencias Informáticas
Cache memories
Variable-Sized Block Cache (VSBC)
Acceso en línea:http://sedici.unlp.edu.ar/handle/10915/9548
http://journal.info.unlp.edu.ar/wp-content/uploads/JCST-Apr07-5.pdf
Aporte de:
SEDICI (UNLP) de Universidad Nacional de La Plata
id I19-R120-10915-9548
record_format dspace
institution Universidad Nacional de La Plata
institution_str I-19
repository_str R-120
collection SEDICI (UNLP)
language Inglés
topic Ciencias Informáticas
Cache memories
Variable-Sized Block Cache (VSBC)
spellingShingle Ciencias Informáticas
Cache memories
Variable-Sized Block Cache (VSBC)
Beg, Azam
Chu, Yul
Utilizing block size variability to enhance instruction fetch rate
topic_facet Ciencias Informáticas
Cache memories
Variable-Sized Block Cache (VSBC)
description In the past, instruction fetch speeds have been improved by using cache schemes that capture the actual program flow. In this paper, we elaborate on the architecture and operation of an instruction cache named Variable-Sized Block Cache (VSBC) that also makes use of the dynamic behavior of a program. Current trace-based cache schemes usually have some instructions stored repeatedly; this redundancy is eliminated in VSBC. Our cache also allows storage of basic blocks of arbitrary sizes, in multiple-way cache structure. An overall comparison of trace miss rate and average trace length shows VSBC to be a better performing cache scheme than TC, using SPECint2000 integer benchmarks.
format Articulo
Articulo
author Beg, Azam
Chu, Yul
author_facet Beg, Azam
Chu, Yul
author_sort Beg, Azam
title Utilizing block size variability to enhance instruction fetch rate
title_short Utilizing block size variability to enhance instruction fetch rate
title_full Utilizing block size variability to enhance instruction fetch rate
title_fullStr Utilizing block size variability to enhance instruction fetch rate
title_full_unstemmed Utilizing block size variability to enhance instruction fetch rate
title_sort utilizing block size variability to enhance instruction fetch rate
publishDate 2007
url http://sedici.unlp.edu.ar/handle/10915/9548
http://journal.info.unlp.edu.ar/wp-content/uploads/JCST-Apr07-5.pdf
work_keys_str_mv AT begazam utilizingblocksizevariabilitytoenhanceinstructionfetchrate
AT chuyul utilizingblocksizevariabilitytoenhanceinstructionfetchrate
bdutipo_str Repositorios
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