Blocked All-Pairs Shortest Paths Algorithm on Intel Xeon Phi KNL Processor: A Case Study

Manycores are consolidating in HPC community as a way of improving performance while keeping power efficiency. Knights Landing is the recently released second generation of Intel Xeon Phi architec- ture.While optimizing applications on CPUs, GPUs and first Xeon Phi’s has been largely studied in the...

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Autores principales: Rucci, Enzo, De Giusti, Armando Eduardo, Naiouf, Marcelo
Formato: Objeto de conferencia
Lenguaje:Inglés
Publicado: 2017
Materias:
Ciencias Informáticas
Xeon Phi
Knights Landing
Floyd-Warshall
Acceso en línea:http://sedici.unlp.edu.ar/handle/10915/63651
Aporte de:
SEDICI (UNLP) de Universidad Nacional de La Plata
id I19-R120-10915-63651
record_format dspace
institution Universidad Nacional de La Plata
institution_str I-19
repository_str R-120
collection SEDICI (UNLP)
language Inglés
topic Ciencias Informáticas
Xeon Phi
Knights Landing
Floyd-Warshall
spellingShingle Ciencias Informáticas
Xeon Phi
Knights Landing
Floyd-Warshall
Rucci, Enzo
De Giusti, Armando Eduardo
Naiouf, Marcelo
Blocked All-Pairs Shortest Paths Algorithm on Intel Xeon Phi KNL Processor: A Case Study
topic_facet Ciencias Informáticas
Xeon Phi
Knights Landing
Floyd-Warshall
description Manycores are consolidating in HPC community as a way of improving performance while keeping power efficiency. Knights Landing is the recently released second generation of Intel Xeon Phi architec- ture.While optimizing applications on CPUs, GPUs and first Xeon Phi’s has been largely studied in the last years, the new features in Knights Landing processors require the revision of programming and optimization techniques for these devices. In this work, we selected the Floyd-Warshall algorithm as a representative case study of graph and memory-bound ap- plications. Starting from the default serial version, we show how data, thread and compiler level optimizations help the parallel implementation to reach 338 GFLOPS.
format Objeto de conferencia
Objeto de conferencia
author Rucci, Enzo
De Giusti, Armando Eduardo
Naiouf, Marcelo
author_facet Rucci, Enzo
De Giusti, Armando Eduardo
Naiouf, Marcelo
author_sort Rucci, Enzo
title Blocked All-Pairs Shortest Paths Algorithm on Intel Xeon Phi KNL Processor: A Case Study
title_short Blocked All-Pairs Shortest Paths Algorithm on Intel Xeon Phi KNL Processor: A Case Study
title_full Blocked All-Pairs Shortest Paths Algorithm on Intel Xeon Phi KNL Processor: A Case Study
title_fullStr Blocked All-Pairs Shortest Paths Algorithm on Intel Xeon Phi KNL Processor: A Case Study
title_full_unstemmed Blocked All-Pairs Shortest Paths Algorithm on Intel Xeon Phi KNL Processor: A Case Study
title_sort blocked all-pairs shortest paths algorithm on intel xeon phi knl processor: a case study
publishDate 2017
url http://sedici.unlp.edu.ar/handle/10915/63651
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AT degiustiarmandoeduardo blockedallpairsshortestpathsalgorithmonintelxeonphiknlprocessoracasestudy
AT naioufmarcelo blockedallpairsshortestpathsalgorithmonintelxeonphiknlprocessoracasestudy
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