SoC-FPGA systems for the acquisition and processing of electroencephalographic signals

Real-time acquisition and processing of electroencephalographic signals have promising applications in the implementation of brain-computer interfaces. These devices allow the user to control a device without performing motor actions, and are usually made up of a biopotential acquisition stage and a...

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Detalles Bibliográficos
Autores principales: Oliva, Matías Javier, García, Pablo Andrés, Spinelli, Enrique Mario, Veiga, Alejandro Luis
Formato: Articulo
Lenguaje:Inglés
Publicado: 2021
Materias:
Ingeniería Electrónica
Biopotentials
Brain-computer interfaces
Digital systems design
SoC-FPGA systems
Steady-state evoked potentials
Acceso en línea:http://sedici.unlp.edu.ar/handle/10915/160818
Aporte de:
SEDICI (UNLP) de Universidad Nacional de La Plata
id I19-R120-10915-160818
record_format dspace
spelling I19-R120-10915-1608182023-11-28T20:08:52Z http://sedici.unlp.edu.ar/handle/10915/160818 SoC-FPGA systems for the acquisition and processing of electroencephalographic signals Oliva, Matías Javier García, Pablo Andrés Spinelli, Enrique Mario Veiga, Alejandro Luis 2021-11-01 2023-11-28T17:44:59Z en Ingeniería Electrónica Biopotentials Brain-computer interfaces Digital systems design SoC-FPGA systems Steady-state evoked potentials Real-time acquisition and processing of electroencephalographic signals have promising applications in the implementation of brain-computer interfaces. These devices allow the user to control a device without performing motor actions, and are usually made up of a biopotential acquisition stage and a personal computer (PC). This structure is very flexible and appropriate for research, but for final users it is necessary to migrate to an embedded system, eliminating the PC from the scheme. The strict real-time processing requirements of such systems justify the choice of a system on a chip fieldprogrammable gate arrays (SoC-FPGA) for its implementation. This article proposes a platform for the acquisition and processing of electroencephalographic signals using this type of device, which combines the parallelism and speed capabilities of an FPGA with the simplicity of a general-purpose processor on a single chip. In this scheme, the FPGA is in charge of the real-time operation, acquiring and processing the signals, while the processor solves the high-level tasks, with the interconnection between processing elements solved by buses integrated into the chip. The proposed scheme was used to implement a brain-computer interface based on steadystate visual evoked potentials, which was used to command a speller. The first tests of the system show that a selection time of 5 seconds per command can be achieved. The time delay between the user’s selection and the system response has been estimated at 343 µs. Instituto de Investigaciones en Electrónica, Control y Procesamiento de Señales Articulo Articulo http://creativecommons.org/licenses/by-sa/4.0/ Creative Commons Attribution-ShareAlike 4.0 International (CC BY-SA 4.0) application/pdf 237-248
institution Universidad Nacional de La Plata
institution_str I-19
repository_str R-120
collection SEDICI (UNLP)
language Inglés
topic Ingeniería Electrónica
Biopotentials
Brain-computer interfaces
Digital systems design
SoC-FPGA systems
Steady-state evoked potentials
spellingShingle Ingeniería Electrónica
Biopotentials
Brain-computer interfaces
Digital systems design
SoC-FPGA systems
Steady-state evoked potentials
Oliva, Matías Javier
García, Pablo Andrés
Spinelli, Enrique Mario
Veiga, Alejandro Luis
SoC-FPGA systems for the acquisition and processing of electroencephalographic signals
topic_facet Ingeniería Electrónica
Biopotentials
Brain-computer interfaces
Digital systems design
SoC-FPGA systems
Steady-state evoked potentials
description Real-time acquisition and processing of electroencephalographic signals have promising applications in the implementation of brain-computer interfaces. These devices allow the user to control a device without performing motor actions, and are usually made up of a biopotential acquisition stage and a personal computer (PC). This structure is very flexible and appropriate for research, but for final users it is necessary to migrate to an embedded system, eliminating the PC from the scheme. The strict real-time processing requirements of such systems justify the choice of a system on a chip fieldprogrammable gate arrays (SoC-FPGA) for its implementation. This article proposes a platform for the acquisition and processing of electroencephalographic signals using this type of device, which combines the parallelism and speed capabilities of an FPGA with the simplicity of a general-purpose processor on a single chip. In this scheme, the FPGA is in charge of the real-time operation, acquiring and processing the signals, while the processor solves the high-level tasks, with the interconnection between processing elements solved by buses integrated into the chip. The proposed scheme was used to implement a brain-computer interface based on steadystate visual evoked potentials, which was used to command a speller. The first tests of the system show that a selection time of 5 seconds per command can be achieved. The time delay between the user’s selection and the system response has been estimated at 343 µs.
format Articulo
Articulo
author Oliva, Matías Javier
García, Pablo Andrés
Spinelli, Enrique Mario
Veiga, Alejandro Luis
author_facet Oliva, Matías Javier
García, Pablo Andrés
Spinelli, Enrique Mario
Veiga, Alejandro Luis
author_sort Oliva, Matías Javier
title SoC-FPGA systems for the acquisition and processing of electroencephalographic signals
title_short SoC-FPGA systems for the acquisition and processing of electroencephalographic signals
title_full SoC-FPGA systems for the acquisition and processing of electroencephalographic signals
title_fullStr SoC-FPGA systems for the acquisition and processing of electroencephalographic signals
title_full_unstemmed SoC-FPGA systems for the acquisition and processing of electroencephalographic signals
title_sort soc-fpga systems for the acquisition and processing of electroencephalographic signals
publishDate 2021
url http://sedici.unlp.edu.ar/handle/10915/160818
work_keys_str_mv AT olivamatiasjavier socfpgasystemsfortheacquisitionandprocessingofelectroencephalographicsignals
AT garciapabloandres socfpgasystemsfortheacquisitionandprocessingofelectroencephalographicsignals
AT spinellienriquemario socfpgasystemsfortheacquisitionandprocessingofelectroencephalographicsignals
AT veigaalejandroluis socfpgasystemsfortheacquisitionandprocessingofelectroencephalographicsignals
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