Cache Sharing Administration for Performance Fairness using D3C Miss Classification in Chip Multi-Processors

This work presents a study of fairness in cache sharing between processes in a chip multiprocessor (CMP). We propose a new algorithm that uses a metric based on the D3C miss classification and LRU Stack Distance, to measure the fairness in the administration of the resources to achieve an increase o...

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Detalles Bibliográficos
Autores principales: Carballal, Claudio A., Hamkalo, José Luis, Cernuschi-Frías, Bruno
Formato: Objeto de conferencia
Lenguaje:Inglés
Publicado: 2011
Materias:
Ciencias Informáticas
Shared Cache
Multi-Process
CMP
Dynamic Cache Administration
Instrumentation
PIN
Acceso en línea:http://sedici.unlp.edu.ar/handle/10915/126119
https://40jaiio.sadio.org.ar/sites/default/files/T2011/HPC/842.pdf
Aporte de:
SEDICI (UNLP) de Universidad Nacional de La Plata

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