Cache Sharing Administration for Performance Fairness using D3C Miss Classification in Chip Multi-Processors
This work presents a study of fairness in cache sharing between processes in a chip multiprocessor (CMP). We propose a new algorithm that uses a metric based on the D3C miss classification and LRU Stack Distance, to measure the fairness in the administration of the resources to achieve an increase o...
Guardado en:
| Autores principales: | , , |
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| Formato: | Objeto de conferencia |
| Lenguaje: | Inglés |
| Publicado: |
2011
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| Materias: | |
| Acceso en línea: | http://sedici.unlp.edu.ar/handle/10915/126119 https://40jaiio.sadio.org.ar/sites/default/files/T2011/HPC/842.pdf |
| Aporte de: |
| id |
I19-R120-10915-126119 |
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| record_format |
dspace |
| institution |
Universidad Nacional de La Plata |
| institution_str |
I-19 |
| repository_str |
R-120 |
| collection |
SEDICI (UNLP) |
| language |
Inglés |
| topic |
Ciencias Informáticas Shared Cache Multi-Process CMP Dynamic Cache Administration Instrumentation PIN |
| spellingShingle |
Ciencias Informáticas Shared Cache Multi-Process CMP Dynamic Cache Administration Instrumentation PIN Carballal, Claudio A. Hamkalo, José Luis Cernuschi-Frías, Bruno Cache Sharing Administration for Performance Fairness using D3C Miss Classification in Chip Multi-Processors |
| topic_facet |
Ciencias Informáticas Shared Cache Multi-Process CMP Dynamic Cache Administration Instrumentation PIN |
| description |
This work presents a study of fairness in cache sharing between processes in a chip multiprocessor (CMP). We propose a new algorithm that uses a metric based on the D3C miss classification and LRU Stack Distance, to measure the fairness in the administration of the resources to achieve an increase of the global IPC of all executed processes. Shared cache miss rate, IPC and bandwidth metrics were considered to analyze the simulation results obtained using three test sets. The obtained results showed that the proposed dynamic management policy compared to Capitalist management policy, has a lower global miss rate in shared cache and lower bandwidth usage for each test set studied and fulfills its objective of managing the shared cache space for every process while improving the overall IPC. |
| format |
Objeto de conferencia Objeto de conferencia |
| author |
Carballal, Claudio A. Hamkalo, José Luis Cernuschi-Frías, Bruno |
| author_facet |
Carballal, Claudio A. Hamkalo, José Luis Cernuschi-Frías, Bruno |
| author_sort |
Carballal, Claudio A. |
| title |
Cache Sharing Administration for Performance Fairness using D3C Miss Classification in Chip Multi-Processors |
| title_short |
Cache Sharing Administration for Performance Fairness using D3C Miss Classification in Chip Multi-Processors |
| title_full |
Cache Sharing Administration for Performance Fairness using D3C Miss Classification in Chip Multi-Processors |
| title_fullStr |
Cache Sharing Administration for Performance Fairness using D3C Miss Classification in Chip Multi-Processors |
| title_full_unstemmed |
Cache Sharing Administration for Performance Fairness using D3C Miss Classification in Chip Multi-Processors |
| title_sort |
cache sharing administration for performance fairness using d3c miss classification in chip multi-processors |
| publishDate |
2011 |
| url |
http://sedici.unlp.edu.ar/handle/10915/126119 https://40jaiio.sadio.org.ar/sites/default/files/T2011/HPC/842.pdf |
| work_keys_str_mv |
AT carballalclaudioa cachesharingadministrationforperformancefairnessusingd3cmissclassificationinchipmultiprocessors AT hamkalojoseluis cachesharingadministrationforperformancefairnessusingd3cmissclassificationinchipmultiprocessors AT cernuschifriasbruno cachesharingadministrationforperformancefairnessusingd3cmissclassificationinchipmultiprocessors |
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Repositorios |
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