Broadband Direct RF Digitization Receivers
This book discusses the trade-offs involved in designing direct RF digitization receivers for the radio frequency and digital signal processing domains. Â A system-level framework is developed, quantifying the relevant impairments of the signal processing chain, through a comprehensive system-level...
Guardado en:
Autor principal: | |
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Formato: | Libro electrónico |
Lenguaje: | Inglés |
Publicado: |
Cham :
Springer International Publishing : Imprint: Springer,
2014.
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Colección: | Analog Circuits and Signal Processing,
121 |
Materias: | |
Acceso en línea: | http://dx.doi.org/10.1007/978-3-319-01150-9 |
Aporte de: | Registro referencial: Solicitar el recurso aquí |
LEADER | 03512Cam#a22004335i#4500 | ||
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100 | 1 | |a Jamin, Olivier. |9 260431 | |
245 | 1 | 0 | |a Broadband Direct RF Digitization Receivers |h [libro electrónico] / |c by Olivier Jamin. |
260 | 1 | |a Cham : |b Springer International Publishing : |b Imprint: Springer, |c 2014. | |
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490 | 1 | |a Analog Circuits and Signal Processing, |x 1872-082X ; |v 121 | |
505 | 0 | |a RF Receiver Architecture State-of-the-Art -- System-Level Design Framework for Direct RF Digitization Receivers -- Application to the System Design of a Multi-Channel Cable Receiver -- Realization & Measurements -- Conclusions & Perspectives. | |
520 | |a This book discusses the trade-offs involved in designing direct RF digitization receivers for the radio frequency and digital signal processing domains.  A system-level framework is developed, quantifying the relevant impairments of the signal processing chain, through a comprehensive system-level analysis. Special focus is given to noise analysis (thermal noise, quantization noise, saturation noise, signal-dependent noise), broadband non-linear distortion analysis, including the impact of the sampling strategy (low-pass, band-pass), analysis of time-interleaved ADC channel mismatches, sampling clock purity and digital channel selection. The system-level framework described is applied to the design of a cable multi-channel RF direct digitization receiver. An optimum RF signal conditioning, and some algorithms (automatic gain control loop, RF front-end amplitude equalization control loop) are used to relax the requirements of a 2.7GHz 11-bit ADC. A two-chip implementation is presented, using BiCMOS and 65nm CMOS processes, together with the block and system-level measurement results. Readers will benefit from the techniques presented, which are highly competitive, both in terms of cost and RF performance, while drastically reducing power consumption.  ·        Provides system-level analysis of direct RF sampling & digitization receivers, from the antenna to the digital channel selection; ·        Includes analysis of broadband non-linearity, applicable for low-pass and band-pass sampling strategies; Describes system-level design of an application-optimized signal conditioner, including a single-inductance multi-slope programmable RF amplitude equalizer, together with its control algorithm and a mixed-signal AGC loop combining RMS and peak detection.  . | ||
650 | 0 | |a Engineering. |9 259622 | |
650 | 0 | |a Microprocessors. |9 259640 | |
650 | 0 | |a Electronic circuits. |9 259798 | |
650 | 2 | 4 | |a Circuits and Systems. |9 259651 |
650 | 2 | 4 | |a Signal, Image and Speech Processing. |9 259616 |
650 | 2 | 4 | |a Processor Architectures. |9 259645 |
776 | 0 | 8 | |i Printed edition: |z 9783319011493 |
856 | 4 | 0 | |u http://dx.doi.org/10.1007/978-3-319-01150-9 |
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