Pipelined Multiprocessor System-on-Chip for Multimedia
This book describes analytical models and estimation methods to enhance performance estimation of pipelined multiprocessor systems-on-chip (MPSoCs). Â A framework is introduced for both design-time and run-time optimizations. For design space exploration, several algorithms are presented to minimize...
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| Otros Autores: | |
| Formato: | Libro electrónico |
| Lenguaje: | Inglés |
| Publicado: |
Cham :
Springer International Publishing : Imprint: Springer,
2014.
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| Materias: | |
| Acceso en línea: | http://dx.doi.org/10.1007/978-3-319-01113-4 |
| Aporte de: | Registro referencial: Solicitar el recurso aquí |
| LEADER | 03369Cam#a22004575i#4500 | ||
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| 020 | |a 9783319011134 | ||
| 024 | 7 | |a 10.1007/978-3-319-01113-4 |2 doi | |
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| 100 | 1 | |a Javaid, Haris. |9 260420 | |
| 245 | 1 | 0 | |a Pipelined Multiprocessor System-on-Chip for Multimedia |h [libro electrónico] / |c by Haris Javaid, Sri Parameswaran. |
| 260 | 1 | |a Cham : |b Springer International Publishing : |b Imprint: Springer, |c 2014. | |
| 300 | |a viii, 169 p. : |b il. | ||
| 336 | |a text |b txt |2 rdacontent | ||
| 337 | |a computer |b c |2 rdamedia | ||
| 338 | |a online resource |b cr |2 rdacarrier | ||
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| 505 | 0 | |a Introduction -- Literature Survey -- Optimisation Framework -- Performance Estimation of Pipelined MPSoCs -- Design Space Exploration of Pipelined MPSoCs -- Adaptive Pipelined MPSoCs -- Power Management in Adaptive Pipelined MPSocs -- Multi-mode Pipelined MPSoCs -- Conclusions and Future Work. | |
| 520 | |a This book describes analytical models and estimation methods to enhance performance estimation of pipelined multiprocessor systems-on-chip (MPSoCs).  A framework is introduced for both design-time and run-time optimizations. For design space exploration, several algorithms are presented to minimize the area footprint of a pipelined MPSoC under a latency or a throughput constraint.  A novel adaptive pipelined MPSoC architecture is described, where idle processors are transitioned into low-power states at run-time to reduce energy consumption. Multi-mode pipelined MPSoCs are introduced, where multiple pipelined MPSoCs optimized separately are merged into a single pipelined MPSoC, enabling further reduction of the area footprint by sharing the processors and communication buffers. Readers will benefit from the authorsâ_T combined use of analytical models, estimation methods and exploration algorithms and will be enabled to explore billions of design points in a few minutes.  ·        Describes the state-of-the-art on pipeline-level parallelism and multimedia MPSoCs; ·        Includes analytical models and estimation methods for performance estimation of pipelined MPSoCs; ·        Covers several design space exploration techniques for pipelined MPSoCs; ·        Introduces an adaptive pipelined MPSoC with run-time processor and power managers; ·        Introduces Multi-mode pipelined MPSoCs for multiple applications.   . | ||
| 650 | 0 | |a Engineering. |9 259622 | |
| 650 | 0 | |a Microprocessors. |9 259640 | |
| 650 | 0 | |a Electronics. |9 259648 | |
| 650 | 0 | |a Microelectronics. |9 259649 | |
| 650 | 0 | |a Electronic circuits. |9 259798 | |
| 650 | 2 | 4 | |a Circuits and Systems. |9 259651 |
| 650 | 2 | 4 | |a Processor Architectures. |9 259645 |
| 650 | 2 | 4 | |a Instrumentation. |9 259652 |
| 700 | 1 | |a Parameswaran, Sri. |9 260421 | |
| 776 | 0 | 8 | |i Printed edition: |z 9783319011127 |
| 856 | 4 | 0 | |u http://dx.doi.org/10.1007/978-3-319-01113-4 |
| 912 | |a ZDB-2-ENG | ||
| 929 | |a COM | ||
| 942 | |c EBK |6 _ | ||
| 950 | |a Engineering (Springer-11647) | ||
| 999 | |a SKV |c 27628 |d 27628 | ||