Using the DEVS paradigm to implement a simulated processor

This work is devoted to present the design and implementation of Alfa-1, a simulated computer with educational purposes. The DEVS formalism was used to attack the complexity of the design, allowing the definition of individual components that can be lately integrated into a modelling hierarchy. The...

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Detalles Bibliográficos
Autores principales:	Daicz, S., Tróccoli, A., Zlotnik, S., Wainer, G.
Formato:	JOUR
Materias:	Algorithms Computer aided instruction Computer architecture Computer simulation Mathematical models Students Discrete event systems specification Inter level interaction Transition junction Computer aided software engineering
Acceso en línea:	http://hdl.handle.net/20.500.12110/paper_02724715_v_n_p58_Daicz
Aporte de:	Biblioteca Digital - Facultad de Ciencias Exactas y Naturales (UBA) de Universidad de Buenos Aires

id	todo:paper_02724715_v_n_p58_Daicz
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spelling	todo:paper_02724715_v_n_p58_Daicz2023-10-03T15:15:15Z Using the DEVS paradigm to implement a simulated processor Daicz, S. Tróccoli, A. Zlotnik, S. Wainer, G. Algorithms Computer aided instruction Computer architecture Computer simulation Mathematical models Students Discrete event systems specification Inter level interaction Transition junction Computer aided software engineering This work is devoted to present the design and implementation of Alfa-1, a simulated computer with educational purposes. The DEVS formalism was used to attack the complexity of the design, allowing the definition of individual components that can be lately integrated into a modelling hierarchy. The tool is designed for the use in Computer Architecture and Organization courses. Its goal is allowing the students to acquire some practice in the design and implementation of hardware components by using simulation. Fil:Daicz, S. Universidad de Buenos Aires. Facultad de Ciencias Exactas y Naturales; Argentina. Fil:Tróccoli, A. Universidad de Buenos Aires. Facultad de Ciencias Exactas y Naturales; Argentina. Fil:Zlotnik, S. Universidad de Buenos Aires. Facultad de Ciencias Exactas y Naturales; Argentina. Fil:Wainer, G. Universidad de Buenos Aires. Facultad de Ciencias Exactas y Naturales; Argentina. JOUR info:eu-repo/semantics/openAccess http://creativecommons.org/licenses/by/2.5/ar http://hdl.handle.net/20.500.12110/paper_02724715_v_n_p58_Daicz
institution	Universidad de Buenos Aires
institution_str	I-28
repository_str	R-134
collection	Biblioteca Digital - Facultad de Ciencias Exactas y Naturales (UBA)
topic	Algorithms Computer aided instruction Computer architecture Computer simulation Mathematical models Students Discrete event systems specification Inter level interaction Transition junction Computer aided software engineering
spellingShingle	Algorithms Computer aided instruction Computer architecture Computer simulation Mathematical models Students Discrete event systems specification Inter level interaction Transition junction Computer aided software engineering Daicz, S. Tróccoli, A. Zlotnik, S. Wainer, G. Using the DEVS paradigm to implement a simulated processor
topic_facet	Algorithms Computer aided instruction Computer architecture Computer simulation Mathematical models Students Discrete event systems specification Inter level interaction Transition junction Computer aided software engineering
description	This work is devoted to present the design and implementation of Alfa-1, a simulated computer with educational purposes. The DEVS formalism was used to attack the complexity of the design, allowing the definition of individual components that can be lately integrated into a modelling hierarchy. The tool is designed for the use in Computer Architecture and Organization courses. Its goal is allowing the students to acquire some practice in the design and implementation of hardware components by using simulation.
format	JOUR
author	Daicz, S. Tróccoli, A. Zlotnik, S. Wainer, G.
author_facet	Daicz, S. Tróccoli, A. Zlotnik, S. Wainer, G.
author_sort	Daicz, S.
title	Using the DEVS paradigm to implement a simulated processor
title_short	Using the DEVS paradigm to implement a simulated processor
title_full	Using the DEVS paradigm to implement a simulated processor
title_fullStr	Using the DEVS paradigm to implement a simulated processor
title_full_unstemmed	Using the DEVS paradigm to implement a simulated processor
title_sort	using the devs paradigm to implement a simulated processor
url	http://hdl.handle.net/20.500.12110/paper_02724715_v_n_p58_Daicz
work_keys_str_mv	AT daiczs usingthedevsparadigmtoimplementasimulatedprocessor AT troccolia usingthedevsparadigmtoimplementasimulatedprocessor AT zlotniks usingthedevsparadigmtoimplementasimulatedprocessor AT wainerg usingthedevsparadigmtoimplementasimulatedprocessor
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Using the DEVS paradigm to implement a simulated processor

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