Using the DEVS paradigm to implement a simulated processor

This work is devoted to present the design and implementation of Alfa-1, a simulated computer with educational purposes. The DEVS formalism was used to attack the complexity of the design, allowing the definition of individual components that can be lately integrated into a modelling hierarchy. The...

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Detalles Bibliográficos
Autores principales: Daicz, Sergio, Troccoli, Alejandro, Zlotnik, Sergio, Wainer, Gabriel A.
Publicado: 2000
Materias:
Algorithms
Computer aided instruction
Computer architecture
Computer simulation
Mathematical models
Students
Discrete event systems specification
Inter level interaction
Transition junction
Computer aided software engineering
Acceso en línea:https://bibliotecadigital.exactas.uba.ar/collection/paper/document/paper_02724715_v_n_p58_Daicz
http://hdl.handle.net/20.500.12110/paper_02724715_v_n_p58_Daicz
Aporte de:
Biblioteca Digital - Facultad de Ciencias Exactas y Naturales (UBA) de Universidad de Buenos Aires
id paper:paper_02724715_v_n_p58_Daicz
record_format dspace
spelling paper:paper_02724715_v_n_p58_Daicz2023-06-08T15:25:17Z Using the DEVS paradigm to implement a simulated processor Daicz, Sergio Troccoli, Alejandro Zlotnik, Sergio Wainer, Gabriel A. Algorithms Computer aided instruction Computer architecture Computer simulation Mathematical models Students Discrete event systems specification Inter level interaction Transition junction Computer aided software engineering This work is devoted to present the design and implementation of Alfa-1, a simulated computer with educational purposes. The DEVS formalism was used to attack the complexity of the design, allowing the definition of individual components that can be lately integrated into a modelling hierarchy. The tool is designed for the use in Computer Architecture and Organization courses. Its goal is allowing the students to acquire some practice in the design and implementation of hardware components by using simulation. Fil:Daicz, S. Universidad de Buenos Aires. Facultad de Ciencias Exactas y Naturales; Argentina. Fil:Tróccoli, A. Universidad de Buenos Aires. Facultad de Ciencias Exactas y Naturales; Argentina. Fil:Zlotnik, S. Universidad de Buenos Aires. Facultad de Ciencias Exactas y Naturales; Argentina. Fil:Wainer, G. Universidad de Buenos Aires. Facultad de Ciencias Exactas y Naturales; Argentina. 2000 https://bibliotecadigital.exactas.uba.ar/collection/paper/document/paper_02724715_v_n_p58_Daicz http://hdl.handle.net/20.500.12110/paper_02724715_v_n_p58_Daicz
institution Universidad de Buenos Aires
institution_str I-28
repository_str R-134
collection Biblioteca Digital - Facultad de Ciencias Exactas y Naturales (UBA)
topic Algorithms
Computer aided instruction
Computer architecture
Computer simulation
Mathematical models
Students
Discrete event systems specification
Inter level interaction
Transition junction
Computer aided software engineering
spellingShingle Algorithms
Computer aided instruction
Computer architecture
Computer simulation
Mathematical models
Students
Discrete event systems specification
Inter level interaction
Transition junction
Computer aided software engineering
Daicz, Sergio
Troccoli, Alejandro
Zlotnik, Sergio
Wainer, Gabriel A.
Using the DEVS paradigm to implement a simulated processor
topic_facet Algorithms
Computer aided instruction
Computer architecture
Computer simulation
Mathematical models
Students
Discrete event systems specification
Inter level interaction
Transition junction
Computer aided software engineering
description This work is devoted to present the design and implementation of Alfa-1, a simulated computer with educational purposes. The DEVS formalism was used to attack the complexity of the design, allowing the definition of individual components that can be lately integrated into a modelling hierarchy. The tool is designed for the use in Computer Architecture and Organization courses. Its goal is allowing the students to acquire some practice in the design and implementation of hardware components by using simulation.
author Daicz, Sergio
Troccoli, Alejandro
Zlotnik, Sergio
Wainer, Gabriel A.
author_facet Daicz, Sergio
Troccoli, Alejandro
Zlotnik, Sergio
Wainer, Gabriel A.
author_sort Daicz, Sergio
title Using the DEVS paradigm to implement a simulated processor
title_short Using the DEVS paradigm to implement a simulated processor
title_full Using the DEVS paradigm to implement a simulated processor
title_fullStr Using the DEVS paradigm to implement a simulated processor
title_full_unstemmed Using the DEVS paradigm to implement a simulated processor
title_sort using the devs paradigm to implement a simulated processor
publishDate 2000
url https://bibliotecadigital.exactas.uba.ar/collection/paper/document/paper_02724715_v_n_p58_Daicz
http://hdl.handle.net/20.500.12110/paper_02724715_v_n_p58_Daicz
work_keys_str_mv AT daiczsergio usingthedevsparadigmtoimplementasimulatedprocessor
AT troccolialejandro usingthedevsparadigmtoimplementasimulatedprocessor
AT zlotniksergio usingthedevsparadigmtoimplementasimulatedprocessor
AT wainergabriela usingthedevsparadigmtoimplementasimulatedprocessor
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