Hybrid Fault Tolerance Techniques to Detect Transient Faults in Embedded Processors
This book describes fault tolerance techniques based on software and hardware to create hybrid techniques. They are able to reduce overall performance degradation and increase error detection when associated with applications implemented in embedded processors. Coverage begins with an extensive disc...
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| Autor principal: | |
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| Otros Autores: | , |
| Formato: | Libro electrónico |
| Lenguaje: | Inglés |
| Publicado: |
Cham :
Springer International Publishing : Imprint: Springer,
2014.
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| Materias: | |
| Acceso en línea: | http://dx.doi.org/10.1007/978-3-319-06340-9 |
| Aporte de: | Registro referencial: Solicitar el recurso aquí |
Tabla de Contenidos:
- Introduction
- Background
- Fault Tolerance Techniques for Processors
- Proposed Techniques to Detect Transient Faults in Processors
- Simulation Fault Injection Experimental Results
- Configuration Bitstream Fault Injection Experimental Results
- Radiation Experimental Results
- Conclusions and Future Work.