The definitive guide to the ARM® Cortex®-M0 and cortex-M0+ processors /
The Definitive Guide to the ARM® Cortex®-M0 and Cortex-M0+ Processors, Second Edition explains the architectures underneath ARM's Cortex-M0 and Cortex-M0+ processors and their programming techniques. Written by ARM's Senior Embedded Technology Manager, Joseph Yiu, the book is packed with e...
Guardado en:
| Autor principal: | |
|---|---|
| Formato: | Libro |
| Lenguaje: | Inglés |
| Publicado: |
Boston, MA :
Elsevier,
c2015.
|
| Edición: | 2nd ed. |
| Materias: | |
| Acceso en línea: | Tapa Indice |
| Aporte de: | Registro referencial: Solicitar el recurso aquí |
| LEADER | 03144cam#a22003495a#4500 | ||
|---|---|---|---|
| 001 | BCCAB018532 | ||
| 008 | 150401s2015####maud###f#b####001#0#eng## | ||
| 005 | 20190816152442.0 | ||
| 003 | AR-BCCAB | ||
| 245 | 1 | 4 | |a The definitive guide to the ARM® Cortex®-M0 and cortex-M0+ processors / |c Joseph Yiu. |
| 250 | # | # | |a 2nd ed. |
| 260 | # | # | |a Boston, MA : |b Elsevier, |c c2015. |
| 300 | # | # | |a xxxi, 746 p. : |b il. ; |c 24 cm. |
| 504 | # | # | |a Incluye referencias bibliográficas e índice. |
| 520 | # | # | |a The Definitive Guide to the ARM® Cortex®-M0 and Cortex-M0+ Processors, Second Edition explains the architectures underneath ARM's Cortex-M0 and Cortex-M0+ processors and their programming techniques. Written by ARM's Senior Embedded Technology Manager, Joseph Yiu, the book is packed with examples on how to use the features in the Cortex-M0 and Cortex-M0+ processors. It provides detailed information on the instruction set architecture, how to use a number of popular development suites, an overview of the software development flow, and information on how to locate problems in the program code and software porting. This new edition includes the differences between the Cortex-M0 and Cortex-M0+ processors such as architectural features (e.g. unprivileged execution level, vector table relocation), new chapters on low power designs and the Memory Protection Unit (MPU), the benefits of the Cortex-M0+ processor, such as the new single cycle I/O interface, higher energy efficiency, better performance and the Micro Trace Buffer (MTB) feature, updated software development tools, updated Real Time Operating System examples using Keil RTX with CMSIS-RTOS APIs, examples of using various Cortex-M0 and Cortex-M0+ based microcontrollers, and much more. Provides detailed information on ARM® Cortex®-M0 and Cortex-M0+ Processors, including their architectures, programming model, instruction set, and interrupt handling Presents detailed information on the differences between the Cortex-M0 and Cortex-M0+ processors Covers software development flow, including examples for various development tools in both C and assembly languages Includes in-depth coverage of design approaches and considerations for developing ultra low power embedded systems, the benchmark for energy efficiency in microcontrollers, and examples of utilizing low power features in microcontrollers |
| 020 | # | # | |a 9780128032770 |
| 100 | 1 | # | |a Yiu, Joseph. |
| 080 | # | # | |a 681.326 |
| 650 | # | 7 | |a Data processors |2 inist |
| 650 | # | 7 | |a Procesador de datos |2 inist |
| 653 | # | # | |a Cortex processors |
| 653 | # | # | |a Processor architecture |
| 653 | # | # | |a Programming technique |
| 653 | # | # | |a Procesadores cortex |
| 653 | # | # | |a Arquitectura de procesadores |
| 653 | # | # | |a Técnica de programación |
| 040 | # | # | |b spa |d arbccab |
| 856 | 4 | 1 | |u https://images-na.ssl-images-amazon.com/images/I/51%2BPo7ULNrL.%5FSX403%5FBO1,204,203,200%5F.jpg |3 Tapa |
| 856 | 4 | 1 | |u http://campi.cab.cnea.gov.ar/tocs/23406.pdf |3 Indice |
| 942 | # | # | |c BK |
| 952 | # | # | |2 udc |a ARBCCAB |b ARBCCAB |d 20170529 |i 23406 |o 681.326 Y64 Ed.2 |p 23406 |t 1 |y BK |
| 952 | # | # | |2 udc |a ARBCCAB |b ARBCCAB |d 20170529 |i 23407 |o 681.326 Y64 Ed.2 Ej.2 |p 23407 |t 2 |y BK |