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01583nam a2200265 a 4500 |
| 003 |
AR-SmUSM |
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20160819144056.0 |
| 008 |
981211s1999 xxua 001 0 eng d |
| 020 |
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|a 1558605576
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| 020 |
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|a 9781558605572
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| 040 |
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|a DLC
|c DLC
|d DLC
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| 082 |
0 |
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|a 621.38152
|b S9664 1999
|2 20
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| 100 |
1 |
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|a Sutherland, Ivan Edward,
|d 1938-
|9 48196
|
| 245 |
1 |
0 |
|a Logical effort :
|b designing fast CMOS circuits /
|c Ivan Sutherland, Robert Sproull, David Harris.
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| 260 |
|
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|a San Francisco, California :
|b Morgan Kaufmann,
|c c1999.
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| 300 |
|
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|a xv, 239 p. :
|b il. ;
|c 24 cm.
|
| 504 |
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|a Incluye referencias bibliográficas (p. [233]) e índice.
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| 505 |
0 |
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|a cap.1. The Method of Logical Effort -- cap. 2. Design Examples -- cap. 3. Deriving the Method of Logical Effort -- cap. 4. Calculating the Logical Effort of Gates -- cap. 5 Calibrating the Model -- cap. 6. Asymmetric Logic Gates -- cap. 7. Unequal Rising and Falling Delays -- cap. 8. Circuit Families -- cap. 9. Forks of Amplifiers -- cap.10. Branches and Interconnect -- cap.11. Wide Structures -- cap.12. Conclusions -- Apéndices : A. Cast of Characters -- B. Reference process parameters -- C. Logical Effort Tools -- D. Solutions.
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| 650 |
|
7 |
|a Semiconductor.
|2 unesco
|9 4020
|
| 650 |
|
7 |
|a Ingeniería eléctrica.
|2 unesco
|9 1693
|
| 700 |
1 |
|
|a Sproull, Robert F.
|9 48192
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| 700 |
1 |
|
|a Harris, David
|q (David F.)
|9 48197
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| 942 |
|
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|2 ddc
|c LIBRO
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| 999 |
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|c 40275
|d 40275
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| 952 |
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|0 0
|1 0
|2 ddc
|4 0
|6 621_381520000000000_S9664_1999
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|8 GRAL
|9 57644
|a 1
|b 1
|d 2016-08-19
|e Compra
|l 0
|o 621.38152 S9664 1999
|p 45275
|r 2016-08-19
|w 2016-08-19
|y LIBRO
|